Data communication system and method, computer program, and recording medium

ABSTRACT

The present invention provides data communication technology for improving the efficiency of cooperation of two or more information processing units (GSM) for more sophisticated processing. According to the present invention, there are provided four GSMs, a sub-MG (merger) for merging data output from the GSMs, and a main MG for merging data output from the four sub-MGs. Data output from the GSMs are stored in parallel in a register on a unit length basis. Then the data stored in the register are serially read on the unit length basis to form serial data. When the serial data contain altered data, auxiliary data for identifying which data have been altered or modified are added to a predetermined portion of the serial data. Then the serial data with the auxiliary data added thereto are output to the main MG. On the other hand, parallel data to be output from a main SYNC to each GSM are copied, and the copies of the same parallel data are propagated over all the GSMs at the same time.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit ofpriorities from the prior Japanese Patent Applications No. 2000-309788filed on Oct. 10, 2000 and No. 2001-306961 filed on Oct. 2, 2001, theentire contents of both of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to data communication technologiesfor making two or more processors cooperate to enable more sophisticatedinformation processing.

[0004] 2. Description of the Related Art

[0005] As processors such as computers grow more sophisticated, the useof such computers sets up the environment for more sophisticatedinformation processing than conventional. Expectations nowadays arerunning high for cooperative operation of two or more image processors,as an example of the above-mentioned processors, to carry out processingfor a large-screen display of motion picture.

[0006] An increase in processing power of each individual processor,however, may not lead to effective use of its processing power except iftransmission of image data, synchronizing signals and other data isproperly performed between the processors cooperating with each other.When image processors cooperate to make a large-screen display of motionpicture, improper data communication therebetween runs a danger ofreducing the number of image frames per second or may result in systemdowntime.

SUMMARY OF THE INVNETION

[0007] It is an object of the present invention to provide a datacommunication system capable of carrying out data communication properto use two or more processors for more sophisticated processing.

[0008] It is another object of the present invention to provide a datacommunication method capable of making full use of processing power ofeach processor when two or more processors are used for cooperativeprocessing.

[0009] According to one aspect of the present invention, there isprovided a data communication system comprising: a register for storingdata which is exchanged between the register and a plurality ofprocessing units for cooperative processing; and control means whichcontrols storing and reading of data into and from the register, whereinthe control means stores data output from each of the plurality ofprocessing units in parallel in the register, while it serially readsthe data from the register on a unit length basis to form serial data,and when the serial data contain data that have been altered from serialdata previously formed, the control means adds auxiliary data foridentifying the altered data to a predetermined portion of the serialdata and outputs to a subsequent-stage processing unit the serial datawith the auxiliary data added thereto.

[0010] It may be arranged that the control means serially reads datafrom the register on the unit length basis to form the serial data atthe time at least one piece of the unit-length data stored in theregister has been altered.

[0011] It may be arranged that the control means further stores data, tobe output from the subsequent-stage processing unit to each of theprocessing units, in parallel in the register, and propagates copies ofthe stored parallel data over all the processing units at the same time.

[0012] According to another aspect of the present invention, there isprovided a data communication system comprising: M first arbitratormeans (where M is a natural number greater than one) each forarbitrating operations of corresponding N processing units (where N is anatural number greater than one), the N processing units cooperating toperform cooperative processing; and second arbitrator means forarbitrating operations of the M first arbitrator means, each of the Mfirst arbitrator means including a first register capable of storing atleast unit-length data output from the N processing units, and thesecond arbitrator means including a second register capable of storingat least data output from the M first arbitrator means, wherein data arestored in parallel in each of the registers and the data stored in eachregister are serially read out to form serial data, such that when theserial data contain data that have been altered from serial datapreviously formed, auxiliary data for identifying which data have beenaltered are added to a predetermined portion of the serial data readfrom at least the first register.

[0013] According to another aspect of the present invention, there isprovided a data communication system comprising: M first arbitratormeans (where M is a natural number greater than one) each forarbitrating operations of corresponding N processing units (where N is anatural number greater than one), the N processing units cooperating toperform cooperative processing; and second arbitrator means forarbitrating operations of the M first arbitrator means, each of the Mfirst arbitrator means including a first register capable of storingunit-length data to be output to each of the N processing units, and thesecond arbitrator means including a second register capable of storingdata of a predetermined size to be output to each of the M firstarbitrator means, wherein copies of the data stored in the secondregister are propagated over all the processing units at the same timethrough the first registers.

[0014] It may be arranged that the processing units cooperate with oneanother to create frame image data with respect to divided images of apredetermined image.

[0015] It may be arranged that each of the processing units includesdrawing processing means for drawing a predetermined image, a pluralityof geometry processing means for performing geometry processing on thebasis of predetermined image display instructions, and an imageinterface which intervenes between the drawing processing means and thegeometry processing means, and the drawing processing means includes abuffer for storing, together with identification information, drawingcontexts that are different in the contents from one another for each ofthe geometry processing means, and means for reading a specific drawingcontext from the buffer in response to input of a drawing instructionfrom the image interface, such that each of the geometry processingmeans performs geometry processing independently on the basis of theimage display instructions and sends to the image interface an imagetransfer request containing the identification information on thedrawing context acquired as a result of the geometry processing togetherwith information indicative of priority given thereto, and the imageinterface receives the image transfer requests from the geometryprocessing means in the order of priority to sequentially input thedrawing instructions to the drawing processing means.

[0016] According to another aspect of the present invention, there isprovided a data communication system which controls storing and readingof data into and from a register provided on a computer network, theregister provided for storing data to be exchanged between the registerand a plurality of processing units for cooperative processing throughthe computer network, the system comprising: first means for storingdata in parallel in the register, the data being output from one of theprocessing units to the other processing unit through the computernetwork; and second means which serially reads the data from theregister on a unit length basis to form serial data, and which, when theserial data contain data that have been altered from serial datapreviously formed, adds auxiliary data for identifying the altered datato a predetermined portion of the serial data and sends the serial datato the other processing unit through the computer network.

[0017] According to another aspect of the present invention, there isprovided a data communication method for carrying out datacommunications between a plurality of processing units for cooperativeprocessing and a subsequent-stage processing unit located at asubsequent stage of the processing units, the method comprising thesteps of: storing unit-length data, output from the processing units, inparallel in a predetermined register; serially reading the unit-lengthdata stored in the register to form serial data, and adding, when theserial data contain data that have been altered from serial datapreviously formed, auxiliary data for identifying the altered data to apredetermined portion of the serial data to send the same to thesubsequent-stage processing unit; and storing data, to be output fromthe subsequent-stage processing unit to the processing units, inparallel in the register, and propagating copies of the stored paralleldata over all the processing units at the same time.

[0018] It may be arranged that the serial data are formed by seriallyreading the stored unit-length data at the time at least one piece ofthe unit-length data stored in parallel in the register has been alteredfrom the serial data previously formed.

[0019] It may be arranged that the processing units and thesubsequent-stage processing unit are computers having communicationcapabilities, the register is provided in any one of the computers, andall the processing units are connected to a computer network so thatdata are exchanged through the computer network.

[0020] According to another aspect of the present invention, there isprovided a computer program for causing a computer to operate as a datacommunication system, the computer having a function to control storingand reading of data into and from a register provided on a computernetwork, the register provided for storing data to be exchanged withother computers for cooperative processing through the computer network,the data communication system comprising: first means for storing datain parallel in the register, the data being output from one of the othercomputers to another of the other computers through the computernetwork; and second means which serially reads the data from theregister on a unit length basis to form serial data, and which, when theserial data contain data that have been altered from serial datapreviously formed, adds auxiliary data for identifying the altered datato a predetermined portion of the serial data and sends the serial datato the other computer through the computer network.

[0021] It may be arranged that the foregoing computer program isrecorded in a computer-readable recording medium.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022]FIG. 1 is a block diagram of an integrated image processingapparatus according to an embodiment of the present invention.

[0023]FIG. 2 is a functional block diagram of a GSM.

[0024]FIG. 3 is a conceptual diagram showing a form of datacommunication between GSBs and a main MG.

[0025]FIG. 4 is a diagram for explaining the form of the datacommunication in detail.

[0026]FIG. 5 is a diagram illustrating a case where data such as aV-SYNC and a trigger are distributed from a main SYNC to each GSM.

[0027]FIG. 6 is a flowchart for explaining steps in a case where frameimage data are send from the GSM to the main MG.

[0028]FIG. 7 is a flowchart for explaining steps in a case where themain SYNC distributes data such as the V-SYNC to the GSM.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] (First Embodiment)

[0030] Description will be made first about an embodiment in which adata communication system according to the present invention is appliedto an integrated image processing apparatus provided with two or moreimage processing units that cooperate to carry out cooperativeprocessing.

[0031] <General Structure>

[0032]FIG. 1 is a block diagram showing the general structure of theintegrated image processing apparatus in this embodiment. The integratedimage processing apparatus includes four image processing units(hereinafter called “GSB”) 100, an integrator or merger (hereinaftercalled “main MG”) 200, a synchronizing circuit (hereinafter called “mainSYNC”) 300, a control unit ((hereinafter called “main CP”) 400, and anetwork control circuit (hereinafter called “main NET”) 500. The main MG200 is located at the subsequent stage of each GSB 100 so that outputdata from the respective GSBs 100 will be merged. The main SYNC 300supplies each GSB 100 with a synchronizing signal (V-SYNC) and otheroperating data. The main CP 400 manages and controls image processingand communication procedures in the entire system. The main NET 500makes all the GSBs 100 cooperate with one another.

[0033] A display unit DP is connected to the output side of the main MG200 so that the results of image processing in the integrated imageprocessing apparatus will be displayed thereon. Timing of sendingvarious data from the main SYNC 300 to each GSM 1 to be described lateris controlled by the main MG 200. The main MG 200, an external storage410 and the main NET 500 are connected to the main CP 400.

[0034] Each GSB 100, the main MG 200, the main SYNC 300, the main CP 400and the main NET 500 are each constituted of an electronic circuitincluding semiconductor devices such as a processor and a memory or acombination of electronic circuits.

[0035] <GSB>

[0036] Each GSB 100 includes four information processing units(hereinafter called “GSM”) 1, a merger (hereinafter called “sub-MG”) 3,a synchronizing circuit (hereinafter called “sub-SYNC”) 4, a controlunit (hereinafter called “sub-CP”) 5, and a network control circuit(hereinafter called “sub-NET”) 6. Each GSM 1 creates frame image datacorresponding to an image data string input thereto. The sub-MG 3 mergesframe image data output from the GSMs 1 into one frame data to outputthe same to subsequent-stage processing. The sub-SYNC 4 supplies eachGSM 1 with a synchronizing signal (V-SYNC) and other operating data. Thesub-CP 5 manages and controls image processing and communicationprocedures in each GSM 1. The sub-NET 6 makes all the GSMs 1 in both thesame GSB and other GSBs cooperate with one another. The frame image dataenable the display unit DP to display an image on the screen thereof.The frame image data contain RGB coordinate values in a frame, an avalue indicative of the transparency of the frame, and a Z valueindicative of which layer the frame concerned corresponds to when two ormore frames are merged.

[0037] Each GSM 1 is equipped with a synchronizing circuit (hereinaftercalled “SYNC-GSM”) 2 which supplies the internal circuitry with asynchronizing signal as an internal operation timing signal.

[0038] The sub-MG 3 and the main MG 200 are each equipped with a dataregister for temporarily storing frame image data to be output.

[0039] The sub-CP 5 is equipped with a demultiplexer (not shown) fordividing the input image data string into four parts and distributing toeach of the four GSMs 1 a quarter of the image data string related to amoving image to be generated. The distribution may take various formsdepending on the application software run on the apparatus. For example,the whole area of an image to be finally displayed may be divided intofour parts, or into four image data strings, each of which is to displaya corresponding layer to be superimposed one upon another for the finalimage. Alternatively, image data that has combined four frames into onemay be divided into four parts.

[0040] The sub-MET 6 is a circuit for passing part or all of the imagedata string between its own GSB and another GSB. The image data stringis passed mainly to balance the load of image processing among the GSBs.

[0041] It should be noted that merging performed by the sub-MG 3 iscarried out in synchronization with an absolute time base that controlsthe operation of all the GSBs. In other words, the sub-MG 3 merges twoor more pieces of frame image data input in synchronization with theabsolute time base to generate one frame image data.

[0042] Each GSB 100 is supplied with an image data string (from the mainCP 400 through the sub-CP 5) and a trigger (from the main SYNC 300through the sub-SYNC 4) as a signal for indicating that image processingis started. The trigger causes all the GSMs 1 to start image processingfor the image data string input to the respective GSBs.

[0043] The SYNC-GSM 2, the sub-SYNC 4 and the main SYNC 300 eachincorporate a data register and two or more counters therein. Eachcounter includes a register for holding its count value, so that aninterrupt occurs when the count value reaches a predetermined value. Ofthese counters, a first counter is to determine the number ofsynchronizing signals for making two or more GSMs 1 operate insynchronization with each other. The first counter is incremented at thefalling edge of an input synchronizing signal (“V-SYNC). Although theV-SINC is asynchronous to the bus clock, since the V-SINC used issampled by a first clock, the increment timing may be varied by oneclock between GSMs. The count value is reset by a reset signal from themain CP 400. However, since the reset signal is coupled with anasynchronous clear terminal of each counter module, a fluctuation of oneclock may occur between GSMs as viewed from the first clock as thereference.

[0044] The second counter is an up counter for measuring a precise timeinterval between V-SYNCs, and is forcefully reset to zero each time itdetects the falling edge of an input synchronizing signal (“V-SYNC).

[0045] <GSM>

[0046] Each GSM 1 creates frame image data corresponding to the inputimage data string at the time at which the V-SYNC is input to theSYNC-GSM 2. Each data piece of the image data string is read andsupplied from the external storage 410 connected to the main CP 400, andprocessed in a predetermined manner to form frame image data.

[0047] In the embodiment, the GSMs 1 serve as the nerve center of theintegrated image processing apparatus. The functional structure of eachGSM 1 according to the embodiment is shown in detail in FIG. 2.

[0048] As shown in FIG. 2, the GSM 1 has two buses, a main bus B1 and asub-bus B2. These buses B1 and B2 are connected to and disconnected fromeach other through a bus interface INT. The main bus B1 is connectedwith a main CPU (Central Processing Unit) 10 and a main memory 11. Themain CPU 10 includes a microprocessor and a VPU 0 20 (where the VPUmeans Vector Processing unit and the VPU 0 is called the “first VPU”below). The main memory 11 is mainly constituted of a RAM (Random AccessMemory). The main bus B1 is also connected with a main DMAC (DirectMemory Access Controller) 12, an MPEG (Motion Picture Experts Group)decoder (MDEC) 13, a VPU 1 (hereinafter called the “second VPU”) 21, anda GIF (Graphical Synthesizer Interface) 30 which serves as an arbiterfor arbitrating between the first VPU 20 and the second VPU 21. Further,the main bus B1 is connected to drawing processing means (“GS”) 31through the GIF 30. The GS 31 is connected to a CRTC (CRT Controller) 33for creating frame image data (video output). The CRTC 33 outputs theframe image data to the sub-MG 3.

[0049] Upon activation, the main CPU 10 reads a bootstrap program from aROM 17 on the sub-bus B2 through the bus interface INT, and runs thebootstrap program to start an operating system. The main CPU 10 alsocooperates with the first VPU 20 to perform geometry processing for 3Dobject data composed of basic graphics or geometries (polygons) such asto process coordinate values of the apexes (representative points) ofthe polygons. A high-speed memory, called an SPR (Scratch Pad RAM), isprovided in the main CPU 10 for temporarily storing processing resultsobtained from the cooperative operation of the main CPU 10 with thefirst VPU 20.

[0050] The first VPU 20 includes two or more operators for computingreal numbers of floating points so that floating-point operations areperformed in parallel by these operators. Thus the main CPU 10 and thefirst VPU 20 cooperate to perform arithmetic processing that requiresdetailed operations on a polygon basis in the geometry processing. As aresult of the arithmetic processing, a display list is created includingas its contents polygon definition information such as a series of apexcoordinates and shading mode information obtained.

[0051] The polygon definition information consists of drawing areasetting information and polygon information.

[0052] The drawing area setting information contains offset coordinatesin a frame buffer address to the drawing area, and coordinate data on adrawing clipping area for canceling the drawing operation in the casewhere the coordinates of a polygon are outside the drawing area.

[0053] The polygon information consists of polygon attribute informationand apex information. The polygon attribute information is to specify ashading mode, an a blending mode, a texture mapping mode, and so on. Theapex information contains coordinates in an apex drawing area,coordinates in an apex texture area, apex colors, and so on.

[0054] The second VPU 21 is constituted in the same manner as the firstVPU 20, that is, it includes two or more operators for computing realnumbers of floating points so that floating-point operations will beperformed in parallel by these operators. Further the second VPU 21creates a display list which includes the operation results as itscontents.

[0055] The first VPU 20 and the second VPU 21, though having the sameconfiguration, serve as geometry engines that share the load ofarithmetic processing different in processing contents. In general, thefirst VPU 20 is assigned processing necessary for complicatedcomputations on something in action such as a character in motion(irregular or free-format geometry processing). On the other hand, thesecond VPU 21 is assigned processing of objects which are simple butneed a large number of polygons such as background buildings (regular orformatted geometry processing). Further, the first VPU 20 performs macrooperations in synchronization with a video rate, while the second VPU 21operates in synchronization with the GS 31. To make the second VPU 21synchronize with the GS 31, the second VPU 21 is equipped with a directpath direct-coupled to the GS 31. On the other hand, the first VPU 20 isclosely coupled to a microprocessor in the main CPU 10 so thatcomplicated processing can easily be programmed.

[0056] The display lists created by the first VPU 20 and the second VPU21 are transferred to the GS 31 through the GIF 30, respectively.

[0057] The GIF 30 arbitrates the collision between the display listscreated in the first VPU 20 and the second VPU 21 during the transferoperation. In the embodiment, the GIF 30 has an additional function forputting these display lists in the order of priority and transferringthem to the GS 31 sequentially in order of precedence. Informationindicative of priority of each display list is generally described in atag field of the display list when the VPU 20 or 21 creates the displaylist, but the priority may be judged independently by the GIF 30.

[0058] The GS 31 holds drawing context information, so that it reads acorresponding drawing context on the basis of identification informationon the image context contained in the display list sent from the GIF 30.The GS 31 then uses the read drawing context to perform rendering fordrawing a polygon on a frame buffer 32. Since the frame memory 32 canalso be used as a texture memory, any pixel image stored on the framebuffer can be pasted on the polygon to be drawn.

[0059] The main DMAC 12 controls not only DMA transfer to each circuitconnected to the main bus B1, but also DMA transfer to each circuitconnected to the sub-bus B2 according to the state of the bus interfaceINT.

[0060] The MDEC 13 operates in parallel with the main CPU 10 todecompress data compressed, for example, in the MPEG (Motion PictureExperts Group) or JPEG (Joint Photographic Experts Group) format.

[0061] The sub-bus B2 is connected with a sub-CPU 14 including amicroprocessor, a sub-memory 15 mainly constituted of a RAM, a sub-DMAC16, and a ROM 17 on which programs such as an operating system arestored. The sub-bus B2 is also connected with a sound processing unit(SPU) 40, which reads tone data accumulated in a sound memory 41 tooutput the same as an audio output, a communication control unit (ATM)50 for receiving and sending data, and an input unit 70.

[0062] The SYNC-GSM 2 is connected to the sub-bus B2, and the sub-NET 6is connected to the ATM 50.

[0063] The input unit 70 includes a video input circuit 73 for taking inimage data from the outside, and an audio input circuit 74 for taking inaudio data from the outside.

[0064] In the embodiment, an image data string is input from the sub-CP5 (distributed from the main CP 400) through the video input circuit 73.The sub-CPU 14 controls various operations according to the programsstored in the ROM 17. The sub-DMAC 16 controls operations such as DMAtransfer to each circuit connected to the sub-bus B2 only when the businterface INT disconnects the main bus B1 from the sub-bus B2.

[0065] <Data Communication System>

[0066] Next, description will be made about a data communication systemincluded in the integrated image processing apparatus.

[0067] Referring first to FIGS. 3 to 5, the concept of datacommunication will be described.

[0068]FIG. 3 shows a from of data communication from the GSBs 100 (GSMs1) toward the main MG 200, and FIG. 4 is a diagram for explaining thedetails of the data communication. FIG. 5 shows a form of datacommunication from the main SYNC 300 toward the GSM 1. The followingillustrates a case where frame image data created as a result of theimage processing are sent from the GSB 100 to the main MG 200, and theV-SYNC is sent from the main SYNC 300 to each GSM 1.

[0069] As shown in FIG. 3, parallel communications occur inside each GSB100. In other words, a predetermined size (e.g., 16 bits) of frame imagedata g (16) are created inside each of the four GSMs 1, and sequentiallystored in an internal register D1 of each GSM 1. The frame image data g(16) are transmitted in parallel to the sub-MG 3. The sub-MG 3 receivesand stores the frame image data g (16) in its internal register D2. Thisparallel communication allows the sub-MG 3 side to receive the frameimage data quickly even if the number of GSMs 1 increases. The size offour pieces of frame image data g (16) stored in the internal registerD2 of the sub-MG 3 is designated as the “unit data length”.

[0070] Frame image data g00 (16) to g03 (16) in the first GSB, g10 (16)to g13 (16) in the second GSB, g20 (16) to g23 (16) in the third GSB,and g30 (16) to g33 (16) in the fourth GSB each form the unit datalength.

[0071] The frame image data are serially transmitted from each GSB 100to the main MG 200, and stored in an internal register D3 of the main MG200. In other words, as shown on the upper right side of FIG. 3, theframe image data are serially read from the internal register D2 of thesub-MG 3 of each GSB 100 on a unit length basis to form serial data.Then the serial data are sequentially stored in the internal register D3of the main MG 200. Thus the capacity of the communication path betweenthe GSB 100 and the main MG 200 can be saved.

[0072] For the serial communication, it is checked whether there are anydata that have been altered or modified from the data stored in theinternal register D3 last time to create auxiliary data (information onthe position and type of data, etc.) for identifying the modified data.The auxiliary data are added to a predetermined portion of the serialdata before output to the main MG 200. In the example of FIG. 4,four-bit auxiliary data H (4) are added to the leading header portion ofeach serial data.

[0073] The frame image data stored in the internal register D2 are readout at the time at least one piece of the frame image data has beenaltered or modified, which prevents wasteful data communications.

[0074] The V-SYNC is distributed from the main SYNC 300 to each GSM sothat the GSMs 1 will be synchronized with one another for imageprocessing. FIG. 5 shows this synchronized state. Each GSM 1 has its ownpath upon which the address to the GSM 1 can be specified. Here, eachsub-SYNC 4 is used as a data mediator alone. The main SYNC 300 holds inits internal register parallel data to be distributed (V-SYNC), makesthe sub-SYNCs 4 copy the parallel data in their internal registers atthe same time, and hence all the GSMs 1 in the GSB 100 concerned copythe same at the same time. Thus the copies of the parallel data arepropagated over all the GSMs 1.

[0075] In the above-mentioned data communication, the internal registerD1 of each GSM 1 in which the frame image data are stored is a framememory 32 or the like, while the register for copying the V-SYNCthereinto is an internal register provided with the above-mentionedfirst counter. The main CPU 10 controls recording of data into theinternal register D1.

[0076] Each sub-MG 3 that is kept under the constant watch of the mainCP 400 carries out reading of the frame image data from the internalregister D1 of each GSM 1 and parallel transmission of the read-outdata. The sub-MG 3 also serves as first arbiter means for arbitratingthe operation of each GSM 1.

[0077] The internal register D2 for temporarily recording the frameimage data sent from each GSM 1 is provided inside the sub-MG 3. Thecapacity of the internal register D2 needs to be high enough to store atleast the data output from the four GSMs at the same time.

[0078] The sub-CP 5 controls recording of the frame image data into theinternal register D2 of the sub-MG 3. On the other hand, the main MG 200that is kept under the constant watch of the main CP 400 carries outreading of data from the internal register D2 of the sub-MG 3 includedin each GSB 100, creation of auxiliary data, and serial transmission tothe main MG 200. The main MG 200 also serves as second arbiter means forarbitrating the operation of each GSB 100.

[0079] The internal register D3 for temporarily recording the frameimage data sent from each GSB 100 is provided inside the main MG 200.The capacity of the internal register D3 needs to be high enough tostore at least the data output from all the GSBs 100 at the same time.

[0080] <Data Communication Process>

[0081] Next, description will be made about a data communication processpractically executed in the integrated image processing apparatusaccording to the embodiment. FIGS. 6 and 7 illustrate the datacommunication procedures.

[0082]FIG. 6 is a flowchart showing steps in a case where frame imagedata created in a GSM 1 are sent to the main MG 200.

[0083] Upon completion of processing within the GSMs, data output fromeach GSM 1 are stored in parallel in the sub-MG 3 inside each GSB 100(step S11 to step S12 if Yes in step S11). If the parallel data from allthe GSMs 1 are completely stored, it is checked whether any alternationor modification has been made to the data already stored (step S13 tostep S14 if Yes in step S13). If any data have been altered or modified,it is checked at which position in the corresponding unit-length datathe modified data is located, and auxiliary data for identifying themodified data are created (step S14 to step S15 if Yes in step S14). Thestored data are serially read out to form serial data. The serial datais then output serially to the main MG 200 with the auxiliary data addedto the leading header portion of the serial data (step S16). In thisembodiment, the auxiliary data represents a position of the modifieddata in the serial data, and thus is placed at the leading headerportion of the serial data as shown in FIG. 4.

[0084] The above-mentioned operational steps are performed for all theGSBs 100. As a result, frame image data processed in all the GSMs 1 ofall the GSBs 100 are stored in parallel in the main MG 200, which makesit possible to display the stored frame image data on the display unitDP at any time. The frame image data stored in the main MG are seriallyoutput to the display unit DP.

[0085]FIG. 7 is a flowchart showing steps in a case where the main SYNC300 distributes data such as the V-SYNC to each GSM 1.

[0086] When data addressed to GSMs occur, parallel data addressed toeach GSM are stored in the internal register of the main SYNC 300 (stepS21 to step S22 if Yes in step S21). The stored parallel data are copiedand the copies of the same parallel data are propagated over all theinternal registers of the four sub-SYNCs 4 at the same time, and overall the four GSMs 1 in each GSB at the same time (step S23). Thus thecopies of the same data can be propagated over all the 16 GSMs at thesame time without any inconsistency, which is effective for cooperativeprocessing of these GSMs 1.

[0087] The cooperative processing of two or more GSMs 1 is thuscoordinated, so that when a large-screen image is to be displayed,processing for making the display can be performed smoothly, thusobtaining a high-quality image on the large screen.

[0088] It should be noted that when the GSMs 1 need to cooperate so asto perform drawing processing, the GSMs are coordinated by givinginstructions to the sub-NET 6 of each GSB 100 via the main NET 500 sothat no inconsistency will occur.

[0089] As discussed above and according to the embodiment, theintegrated image processing apparatus is such that frame image dataoutput from two or more GSMs 1 are stored in parallel. The frame imagedata stored are serially read to form serial data to be sent to the mainMG 200. Auxiliary data are added to the leading header portion of theserial data for identifying modified data in the serial data. Theabove-mentioned configuration has the advantage of immediatelyidentifying modified data while saving the capacity of the communicationpath required for the data communication.

[0090] Further, data (V-SYNC) for each internal register are copied andthe copies of the same data are propagated from the main SYNC 300 overall the GSMs 1 at the same time. This makes it possible for two or moreGSMs 1 to operate at the same time without any inconsistency.

[0091] The frame image data created in the four GSBs 100 are output byreferring to the absolute time base of each GSB. However, since theabsolute time base is uniquely assigned to each GSB, slightoutput-to-output variation would result. This means that the absolutetime base of each GSB 100 corresponds to a relative time base as seenfrom the entire integrated image processing apparatus. The use of themain SYNC 300 to carry out the above-mentioned data communicationsenables the above-mentioned relative time base to accord with the timebase unique to the integrated image processing apparatus. Thus the datamerged in the main MG 200 are controlled by the absolute time base ofthe integrated image processing apparatus.

[0092] In the embodiment, when frame image data from a GSB 100 becomechipped, the main MG 200 merges all the frame image data along theabsolute time base without compensation for the missing image signal.The frame image data thus created are output and displayed on thedisplay unit DP. Since two or more GSMs 1 are used to create an image,image processing can be smoothly performed even if a large-screendisplay of the image is to be made, thereby obtaining a high-qualityimage on the large screen.

[0093] Further, in the embodiment, the main CP 400 and the sub-CP 5, andthe main MG 200 and the sub-MG 3 can be configured in the same manner,respectively, which makes it possible to perform sophisticated imageprocessing, for example, for obtaining a high-quality, large-screenimage using a simple design technique. The number of GSMs 1 in each GSB100 or the number of GSBs 100 can be arbitrarily decided. Variations inthe number may be decided according to the tradeoff between quality andcost, which can reduce its design limits. For example, if the number ofGSMs 1 increases, the cost will rise but the image quality obtained willbecome higher.

[0094] Although in the embodiment description was made about datacommunication technology for image processing, the data communicationtechnology can also be applied to information processing of other typesthan the image processing such as processing for generating sound. Forexample, more delicate, high-quality sound such as in an orchestraconcert can be reproduced. In this case, two or more pieces of data forgenerating sound are individually processed in each GSM 1. Further, aform of complex processing can be considered in which image processingis linked with sound generation. As shown in FIG. 2, the use of GSMs 1according to the embodiment enables such complex processing. When theinformation processing involves sound generation, sound data obtained inthe processing become signals for outputting tones from a predeterminedspeaker or speakers. Then the sound data are output in synchronizationwith the above-mentioned frame image data by means of theabove-mentioned sub-MGs 3 and the main MG 200. It should be noted thatthe sound data to each GSM 1 are input from an audio input circuit 74and output from an SPU 40 as shown in FIG. 2.

[0095] (Second Embodiment)

[0096] The first embodiment described an exemplary data communicationsystem included in the integrated image processing apparatus providedwith two or more image processing units that cooperate to carry outcooperative processing, but the present invention can be implemented ina network type data communication system.

[0097] In other words, the present invention can be implemented in thefollowing network type data communication system. In this case, two ormore information processing terminals installed at completely differentlocations are connected through a computer network such as the Internet.The information processing terminals can operate as the processingunits, the arbitrator means, the register and the control meansaccording to the present invention while inter-exchanging data amongthese information terminals through the computer network.

[0098] Some of the information processing terminals serve as the GSBs100 described in the first embodiment. The other information processingterminals share the following features: the main MG 200 for mergingoutput data of the information processing terminals serving as the GSBs100, the main SYNC 300 for supplying the synchronizing signal (V-SINC)and other operating data to each GSB 1, the main CP 400 for managing andcontrolling image processing and communication procedures, and the mainNET 500 for making all the GSBs 100 cooperate with one another.

[0099] The output side of the information processing terminal serving asthe main MG 200 is connected to a display unit. The informationprocessing terminal serving as the main MG 200 controls the timing ofsending various data from the main SYNC 300 to each GSB 100. On theother hand, the information processing terminal serving as the main CP400 is connected to the information processing terminals serving as themain MG 200, the external storage and the main NET, respectively.

[0100] The network type data communication system thus configuredoperates in the same manner as that in the first embodiment.

[0101] (Third Embodiment)

[0102] Further, the present invention can be implemented in a datacommunication system which controls storing and reading of data into andfrom a register provided on a computer network so that the data to beexchanged between the above-mentioned GSMs for cooperative processingthrough the computer network will be stored in the register.

[0103] Such a data communication system may include a server connectableto the computer network and an external storage accessible to theserver. In this case, the server (and a CPU incorporated in the server)reads and executes a computer program recorded on a predeterminedrecording medium to form not only a register for data communication inthe external storage, but also a feature as a main control unit insidethe server.

[0104] The main control unit includes two functional modules.

[0105] The first functional module has the function of acquiring data tobe output from any one of the GSMs to the other GSMs (the otherinformation processing terminals) through the computer network andstoring the same in parallel in the above-mentioned register.

[0106] The second functional module has the function of serially readingdata from the above-mentioned register on a unit length basis to formserial data. When the serial data contain data that have been altered ormodified from the serial data previously formed, the second functionalmodule adds auxiliary data for identifying which data have been alteredor modified to a predetermined portion of the serial data. Then thesecond functional module sends the serial data with the auxiliary dataadded thereto to the other information processing terminals as the otherGSMs through the computer network.

[0107] The data communication system thus configured operates in thesame manner as those in the first and second embodiments, except thatthe control unit independently controls storing and reading of data intoand from the register, which can also avoid inconsistencies incooperative processing of two or more GSMs.

[0108] As described above and according to the present invention,processing can be performed without any inconsistency even if two ormore processing units are used. If the processing units are imageprocessing units, two or more frames of image data can be output at thesame time, which makes it possible to obtain a high-quality image on alarge screen compared to the conventional.

What is claimed is:
 1. A data communication system comprising: aregister for storing data which is exchanged between said register and aplurality of processing units for cooperative processing; and controlmeans which controls storing and reading of data into and from saidregister, wherein said control means stores data output from each of theplurality of processing units in parallel in said register, while itserially reads the data from said register on a unit length basis toform serial data, and when the serial data contain data that have beenaltered from serial data previously formed, said control means addsauxiliary data for identifying the altered data to a predeterminedportion of the serial data and outputs to a subsequent-stage processingunit the serial data with the auxiliary data added thereto.
 2. Thesystem according to claim 1, wherein said control means serially readsdata from said register on the unit length basis to form the serial dataat the time at least one piece of the unit-length data stored in saidregister has been altered.
 3. The system according to claim 1, whereinsaid control means further stores data, to be output from thesubsequent-stage processing unit to each of the processing units, inparallel in said register, and propagates copies of the stored paralleldata over all the processing units at the same time.
 4. The systemaccording to claim 1, wherein said processing units cooperate with oneanother to create frame image data with respect to divided images of apredetermined image.
 5. The system according to claim 1, wherein each ofsaid processing units includes drawing processing means for drawing apredetermined image, a plurality of geometry processing means forperforming geometry processing on the basis of predetermined imagedisplay instructions, and an image interface which intervenes betweensaid drawing processing means and said geometry processing means, andsaid drawing processing means includes a buffer for storing, togetherwith identification information, drawing contexts that are different inthe contents from one another for each of said geometry processingmeans, and means for reading a specific drawing context from said bufferin response to input of a drawing instruction from said image interface,such that each of said geometry processing means performs geometryprocessing independently on the basis of the image display instructionsand sends to said image interface an image transfer request containingthe identification information on the drawing context acquired as aresult of the geometry processing together with information indicativeof priority given thereto, and said image interface receives the imagetransfer requests from said geometry processing means in the order ofpriority to sequentially input the drawing instructions to said drawingprocessing means.
 6. A data communication system comprising: M firstarbitrator means (where M is a natural number greater than one) each forarbitrating operations of corresponding N processing units (where N is anatural number greater than one), said N processing units cooperating toperform cooperative processing; and second arbitrator means forarbitrating operations of the M first arbitrator means, each of said Mfirst arbitrator means including a first register capable of storing atleast unit-length data output from said N processing units, and saidsecond arbitrator means including a second register capable of storingat least data output from said M first arbitrator means, wherein dataare stored in parallel in each of said registers and the data stored ineach register are serially read out to form serial data, such that whenthe serial data contain data that have been altered from serial datapreviously formed, auxiliary data for identifying which data have beenaltered are added to a predetermined portion of the serial data readfrom at least said first register.
 7. The system according to claim 6,wherein said processing units cooperate with one another to create frameimage data with respect to divided images of a predetermined image. 8.The system according to claim 6, wherein each of said processing unitsincludes drawing processing means for drawing a predetermined image, aplurality of geometry processing means for performing geometryprocessing on the basis of predetermined image display instructions, andan image interface which intervenes between said drawing processingmeans and said geometry processing means, and said drawing processingmeans includes a buffer for storing, together with identificationinformation, drawing contexts that are different in the contents fromone another for each of said geometry processing means, and means forreading a specific drawing context from said buffer in response to inputof a drawing instruction from said image interface, such that each ofsaid geometry processing means performs geometry processingindependently on the basis of the image display instructions and sendsto said image interface an image transfer request containing theidentification information on the drawing context acquired as a resultof the geometry processing together with information indicative ofpriority given thereto, and said image interface receives the imagetransfer requests from said geometry processing means in the order ofpriority to sequentially input the drawing instructions to said drawingprocessing means.
 9. A data communication system comprising: M firstarbitrator means (where M is a natural number greater than one) each forarbitrating operations of corresponding N processing units (where N is anatural number greater than one), said N processing units cooperating toperform cooperative processing; and second arbitrator means forarbitrating operations of the M first arbitrator means, each of said Mfirst arbitrator means including a first register capable of storingunit-length data to be output to each of said N processing units, andsaid second arbitrator means including a second register capable ofstoring data of a predetermined size to be output to each of said Mfirst arbitrator means, wherein copies of the data stored in said secondregister are propagated over all said processing units at the same timethrough said first registers.
 10. The system according to claim 9,wherein said processing units cooperate with one another to create frameimage data with respect to divided images of a predetermined image. 11.The system according to claim 9, wherein each of said processing unitsincludes drawing processing means for drawing a predetermined image, aplurality of geometry processing means for performing geometryprocessing on the basis of predetermined image display instructions, andan image interface which intervenes between said drawing processingmeans and said geometry processing means, and said drawing processingmeans includes a buffer for storing, together with identificationinformation, drawing contexts that are different in the contents fromone another for each of said geometry processing means, and means forreading a specific drawing context from said buffer in response to inputof a drawing instruction from said image interface, such that each ofsaid geometry processing means performs geometry processingindependently on the basis of the image display instructions and sendsto said image interface an image transfer request containing theidentification information on the-drawing context acquired as a resultof the geometry processing together with information indicative ofpriority given thereto, and said image interface receives the imagetransfer requests from said geometry processing means in the order ofpriority to sequentially input the drawing instructions to said drawingprocessing means.
 12. A data communication system which controls storingand reading of data into and from a register provided on a computernetwork, said register provided for storing data to be exchanged betweensaid register and a plurality of processing units for cooperativeprocessing through the computer network, said system comprising: firstmeans for storing data in parallel in the register, the data beingoutput from one of the processing units to the other processing unitthrough the computer network; and second means which serially reads thedata from the register on a unit length basis to form serial data, andwhich, when the serial data contain data that have been altered fromserial data previously formed, adds auxiliary data for identifying thealtered data to a predetermined portion of the serial data and sends theserial data to the other processing unit through the computer network.13. A data communication method for carrying out data communicationsbetween a plurality of processing units for cooperative processing and asubsequent-stage processing unit located at a subsequent stage of saidprocessing units, said method comprising the steps of: storingunit-length data, output from said processing units, in parallel in apredetermined register; serially reading the unit-length data stored inthe register to form serial data, and adding, when the serial datacontain data that have been altered from serial data previously formed,auxiliary data for identifying the altered data to a predeterminedportion of the serial data to send the same to the subsequent-stageprocessing unit; and storing data, to be output from thesubsequent-stage processing unit to said processing units, in parallelin said register, and propagating copies of the stored parallel dataover all the processing units at the same time.
 14. The method accordingto claim 13, wherein the serial data are formed by serially reading thestored unit-length data at the time at least one piece of theunit-length data stored in parallel in the register has been alteredfrom the serial data previously formed.
 15. The method according toclaim 13, wherein the processing units and the subsequent-stageprocessing unit are computers having communication capabilities, theregister is provided in any one of the computers, and all the processingunits are connected to a computer network so that data are exchangedthrough the computer network.
 16. A computer program for causing acomputer to operate as a data communication system, the computer havinga function to control storing and reading of data into and from aregister provided on a computer network, said register provided forstoring data to be exchanged with other computers for cooperativeprocessing through the computer network, said data communication systemcomprising: first means for storing data in parallel in the register,the data being output from one of said other computers to another ofsaid other computers through the computer network; and second meanswhich serially reads the data from the register on a unit length basisto form serial data, and which, when the serial data contain data thathave been altered from serial data previously formed, adds auxiliarydata for identifying the altered data to a predetermined portion of theserial data and sends the serial data to the other computer through thecomputer network.
 17. A computer-readable recording medium recording thecomputer program according to claim 16.